MR-PIPA: An Integrated Multilevel RRAM (HfO_<i>x</i>)-Based Processing-In-Pixel Accelerator

This work paves the way to realize a processing-in-pixel (PIP) accelerator based on multilevel HfOx resistive random access memory (RRAM) as flexible, energy-efficient, and high-performance solution for real-time smart image processing at edge devices. The proposed design intrinsically implements supports coarse-grained convolution operation in low-bit-width neural networks (NNs) leveraging novel compute-pixel with nonvolatile weight storage sensor side. Our evaluations show that such can remarkably reduce power consumption of data conversion transmission an off-chip processor maintaining accuracy compared recent in-sensor computing designs. design, namely integrated RRAM (HfOx)-based (MR-PIPA), achieves frame rate 1000 efficiency ~1.89 TOp/s/W, while it substantially reduces energy by ~84% baseline cost minor degradation.